Experienced engineer, 20 years, FPGA/ASIC, DO-254, Verilog, 15 patents related to design, mainly looking for verification or bring up work. Will arrive in Ottawa in middle of June.
Discount for either of the following:
part time work (20 hours/week)
project bring up work ( 80-100 hours/week in lab for a month or two)
Especially good at bringing large, unfamiliar systems up quickly and diagnosing issues between hardware and software. Works well in team environment, english native language.